Conventional HEMT (high electron mobility transistor) devices fabricated in GaN technology are generally characterized by a negative threshold voltage, i.e. a current can flow between source and drain terminals even without the application of a voltage to the gate electrode. Indeed, a thin inversion layer is automatically created between the source and drain terminals due to strain and polarization effects, even without applying any voltage to the gate electrode. In this case, the device is said to be a “normally-on” transistor.
Such a feature, which is an intrinsic property of GaN technology, restricts the range of applications of GaN technology to those where a power supply is available to generate the negative voltages necessary to turn off the GaN transistor. Moreover, it complicates the design of the circuitry needed to drive GaN transistors.
Another common problem associated with field effect transistors, which can also be applied to GaN technology, are so-called short channel effects which result in increased leakage current when the source-to-drain voltage is increased, even when the transistor is in voltage blocking mode. Increased leakage current becomes more problematic as the device dimensions are scaled in order to achieve higher integration density.
Moreover, power transistors generally suffer from high sub-threshold slope which intrinsically limits the maximum speed of the transistor during switching operation. The sub-threshold slope gives an indication as to how fast a transistor can switch from the off-state to the on-state condition.
The tunnel transistor overcomes the speed limits and short channel effects described above. The main idea behind a tunnel transistor is to replace the main mechanism of carrier thermionic emission over a potential energy barrier, which controls current conduction in conventional field effect transistors, with a tunnelling process through a very thin potential barrier. In this way, short channel effects can be completely suppressed and extremely low sub-threshold slopes achieved e.g. a few mV/dec instead of hundreds mV/dec for Si-based tunnel FETs. High-volume production of tunnel transistors is mainly limited by the immaturity of the technology and the low current drive capability of tunnel transistors which significantly lags that of conventional silicon MOSFETs (metal oxide semiconductor field effect transistors).
In a typical Si-based tunnel FET, a positive voltage is applied to the gate electrode which causes an inversion layer to connect the n-type drain region with the p-type source region. In this way, a very abrupt transition between two opposite highly doped regions occurs and a very thin energy barrier is created. Electrons can tunnel (cross) this thin barrier when a potential difference is applied between the source and drain terminals. This device concept is also characterized by an ambipolar behavior. Indeed, if a negative voltage is applied to the gate electrode, a hole accumulation layer connects the source and drain regions and a tunnelling barrier is created, this time, at the interface between the hole accumulation channel and the n-type drain region.
Conventional tunnel FETs require very highly doped source/drain regions and very steep doping profiles in order for the tunnelling barrier to be very thin and for the tunnelling mechanism to occur efficiently. Moreover, in conventional tunnel FETs, the tunnelling mechanism occurs at the interface between silicon and oxide where defects strongly influence the device performance and reliability in an adverse manner.